January 03, 2013

One Second Counter in VHDL for spartan3E

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Hi friends,
This is the vhdl code for LED blinking at 1 sec exactly.
I have a Papilio one which is running at 32MHz.
So all I had to do is count 32million (1111010000100100000000000 in binary) clock pulses to get one second.
Then I toggled the LED pin.

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity main is
     port (
              clk:in std_logic;
              led1:out std_logic;
              led2:out std_logic
              );           
    
end main;

architecture Behavioral of main is
     signal counter: std_logic_vector(26 downto 0) := (others =>'0');
     signal bit1:std_logic :='0';
     signal bit2:std_logic :='0';

begin
     timer_process:process(clk)
     begin
          if rising_edge(clk) then
              if (counter(24 downto 0) = "1111010000100100000000000") then --count upto 32M
                   led1 <= bit1;
                   led2 <= bit2;
                   counter <= (others =>'0') ;
                   bit1 <= not bit1;
                   bit2 <= not bit2;
              else
                   counter <= counter+1;
              end if;
          end if;
     end process;
end Behavioral;

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January 02, 2013

LED blinking with Spartan3E



Hi friends,
I just bought Papilio one FPGA development board and started to learn Spartan3E.
Here is a cool video to start with Xilinx  ISE development.


 The person explained well with another Spartan3E board but most of things remain the same.....

Here is the counter designed for Papilio One in VHDL.
Here the counter is a 30 bit counter and 22nd and 23rd pins are connected to led. Actually i was not aware when I can see LED blinking so I set a large counter and experimented by trial.





library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.all;

entity LEDs is
             Port (
                          LED1 : out STD_LOGIC;
                          LED2 : out STD_LOGIC;
                          LED3 : out STD_LOGIC;
                          clk : in STD_LOGIC
                      );
end LEDs;
architecture Behavioral of LEDs is
             signal counter : STD_LOGIC_VECTOR(29 downto 0) := (others => '0');
             begin
        
                 clk_proc: process(clk)
                 begin
                      if rising_edge(clk) then
                               counter <= counter+1;
                               LED1 <= counter(23);
                               LED2 <= counter(22);
                               LED3 <= '1';
                      end if;
                 end process;
end Behavioral;

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