Hi friends,
I just bought Papilio one FPGA development board and started to learn Spartan3E.
Here is a cool video to start with Xilinx ISE development.
The person explained well with another Spartan3E board but most of things remain the same.....
Here is the counter designed for Papilio One in VHDL.
Here the counter is a 30 bit counter and 22nd and 23rd pins are connected to led. Actually i was not aware when I can see LED blinking so I set a large counter and experimented by trial.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.all;
entity LEDs is
Port (
LED1
: out STD_LOGIC;
LED2
: out STD_LOGIC;
LED3
: out STD_LOGIC;
clk : in STD_LOGIC
);
end LEDs;
architecture Behavioral
of LEDs is
signal
counter : STD_LOGIC_VECTOR(29 downto 0) := (others
=> '0');
begin
clk_proc:
process(clk)
begin
if
rising_edge(clk) then
counter <= counter+1;
LED1 <= counter(23);
LED2 <= counter(22);
LED3 <= '1';
end
if;
end
process;
end Behavioral;
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